TSMC unveils 2nm technology – up to 15% performance improvement and 30% reduction in energy consumption
As you know, the smaller the node manufacturing process, the more transistors used in the chip. This is important because increasing the number of transistors means that a chipset is more powerful and more efficient in terms of energy consumption. 2nm lithography is the first generation of TSMC products, in which GAAFET transistors (abbreviated Gate All Around Field Effect Transistors) will be used, which the Taiwanese company calls nanosheet-based transistors. This lithography enables chip designers to significantly reduce the power consumption of products; But the increase in speed and transistor density in this technology will be less noticeable.
N2 is a completely new platform where EUV lithography is widely used and GAAFET or nanosheet transistors are used. This transistor structure has important advantages such as reducing current leakage and the ability to adjust the channel width.
Current leakage means the gradual discharge of energy and charging of the capacitor, which causes parts such as transistors and diodes that are connected to the capacitor to pass a small amount of current even when it is off. GAAFET or nanosheet transistors are equipped with channels in which the gate is placed on four sides of the channel, which reduces leakage and energy loss. In addition, the channels of these transistors can be widened to increase the drive current and improve performance, or their width can be reduced and narrowed to reduce energy consumption.
also in order to provide higher processing power and reduce energy consumption A system known as backside power delivery is used in these transistors, which according to TSMC is one of the best solutions to deal with the resistance in the back end of line or BEOL (abbreviated back end of line).
2 nm lithography It seems relatively promising in terms of operational features; Because TSMC promises that this technology will increase the performance of the chip by 10 to 15 percent with the same energy consumption and number of transistors as N3E. On the other hand, with the same frequency and complexity as the previous generation, reduce energy consumption by 25-30%. However, the density of chips produced with this lithography will only increase by about 1.1 times compared to N3E technology.
The improved performance and reduced power consumption in 2nm lithography, unlike N3E, is largely in line with previous TSMC trends. But the so-called chip density improvement, which should reflect the increase in the number of transistors per square millimeter, is only slightly more than 10% compared to N3E, which is not a significant increase; Especially considering that the number of N3E transistors is slightly less than N3 lithography. Hence, a 10% improvement in chip density over the next three years will not be good news for GPUs and other chips that rely on rapidly increasing transistor counts.
Considering that TSMC has From producing N2-based chips, it will use optimized N3S lithography. It seems that the Taiwanese chipmaker will use two different manufacturing technologies based on different types of transistors, whose transistor densities are very close to each other; A problem that has not happened before.
Among the features of the new platform, the Taiwanese company mentions another feature called “chip integration”, which most likely means that smart product manufacturers can combine the chipset built with N2 technology with multi-chip packages that are compatible with Different lithographs are made, they form a whole. This feature is important because the scale of transistor density is decreasing and the cost of new lithography is increasing. For this reason, the use of multi-chip packages will be popular in the coming years, and developers will use it to optimize their design and costs.
The number one chip manufacturer in the world has considered various applications for N2 lithography, among which we can mention mobile chipsets, high-performance CPUs and GPUs. According to the announcement of the Taiwanese company, mass production of the first chips based on 2nm technology will begin in the second half of 2025, and thus, if everything goes according to plan, by the end of 2025 and the beginning of 2026, we will see the presence of this chipset in smart products. we will be; Although, according to news sources, TSMC will offer several chips with 3nm technology by then, among which N3P (focusing on performance improvement) and N3S (focusing on chip density) can be mentioned.