The production of Samsung’s 3nm chips will begin in 2022
before the release of the new roadmap Samsung, concerns were raised about the health of Samsung’s 3 nm lithography; Initially, it was supposed that the risk production using this lithography would take place in 2020 and mass production in 2021. But the evidence shows that this has been delayed for at least a year. Interestingly, Dr. Chidi Chidambaram, vice president of engineering at Qualcomm, estimated the GAA lithography technology to be operational between 2023 and 2024.
According to a Samsung official, the company is in talks with its customers regarding 3GAE lithography, and chips with this lithography are expected to reach mass production from 2022. Post-3GAE lithography – which Samsung has chosen to call 3GAP – remains on Samsung’s roadmap, with mass production (as planned) beginning in 2023. Mind you, the roadmap we are talking about was unveiled during Foundry Forum 2021 in China. Of course, Samsung updated its technology roadmap and republished it on Baidu and Weibo.
Regarding the use of the older FinFET architecture, Samsung has added 5LPP and 4LPP lithography to its roadmap, which are expected to be operational in 2021 and 2022, respectively. When unveiling the 3GAE and 3GAP lithographies in May 2019, Samsung announced that these lithographies can improve chipset performance by 35% and reduce power consumption by 50% compared to 7LPP (which is currently considered a previous-generation lithography). .
In the same year 2019, Samsung began mass production of chips using lithography 3GAA had predicted late 2021, but with that being pushed back to 2022, it could be attributed to a delay on Samsung’s part or a miscalculation by the company. Either way, this hiatus didn’t matter much to Samsung, because Samsung’s early lithographs weren’t yet widely used by manufacturers.
A few days ago, Samsung unveiled a 3nm chip with 3GAA lithography in the tape-out stage. Tape-out is actually the last stage of the design cycle of a chipset, which ends in one of the following two outcomes: either the chip works well with this design, or the design fails. When the design is not successful, applying some small corrections and if needed, a general revision of the design, can be a solution.